1. Field of the Invention
The present invention relates to digital memory management systems and, more specifically, to a system that manages partially uniform memory configurations in a memory space.
2. Description of the Prior Art
Most computer systems employ a memory space for the storage of information. Part of the memory space will typically include an array of dynamic random access memory (DRAM) devices that are organized into one of several ports. Typically, each port will include several ranks into which each DRAM device is placed. One exemplary system includes four memory ports, with 16 memory ranks per memory port, into which any one of six different DRAM technologies may be plugged. In such a system, there millions of possible plug configurations.
To realize the best performance, it is best to interleave as much of the memory as possible. For uniform plug configurations, such as a two-port or four-port configurations with matched DRAM technology and matched plug order, the same address map is used for all accesses. In such configurations, address translation can be performed quite easily and quickly, thereby resulting in minimum latency. Non-uniform plug configurations have either non-matched DRAM technology or non-matching plug order across the populated ports. In non-uniform configurations, translating an address requires first comparing the address against various boundaries to determine which “interleave region” that the address belongs to. Once the interleave region is determined, address translation logic must adjust the address to fit the map for that region. The adjusted address is then compared against the base offsets for each memory rank, extracting the DRAM technology corresponding to the matching base offset. Using the extracted DRAM technology, the adjusted address is then applied to the corresponding map for that technology to arrive ultimately at the actual DRAM address. This is referred to as a “full translation.”
Existing systems allow use of a “homogeneous technology mode” (HT mode), when the plug configuration is a matched 1-, 2-, or 4-port configuration with all DRAM technologies matching and all ranks populated contiguously from 0 to n. All other cases require taking a full address translation path (i.e., employing a non-HT mode).
There are many non-uniform configurations that have a portion of the memory that is uniform. These often result when the user adds a memory device thinking that the added memory will improve performance. In this situation, the user may not realize that by making a portion of the configuration non-uniform, every memory access will require a full translation, which ultimately degrades system performance.
Therefore, there is a need for a system that employs fast address translation for addresses within a uniform portion of a non-uniform memory space.